The recently introduced SiGe BiCMOS technology enables a tremendous increase in on-chip signal bandwidth in the areas of analog and mixed signal (AMS) design. Undoubtedly, the increased bandwidth capability has created new chip design challenges.
FIG. 1 is a flow chart of prior art integrated circuit design flow. As is common in AMS design practice, a designer starts with an architecture and floor plan definitions stage 12. During stage 12, the project is defined on the system level, which means that major design blocks and their locations may be determined.
Next is the schematic design stage 14, wherein a schematic of the design is drawn up. In schematic stage 14, the design components such as transistors and resistors may be defined, and may be connected by ideal wires. Typically at this stage, the wires and connections may be defined without considering the wire delay, signal distortion across the wire, etc.
During a physical design stage 16, the actual physical location (e.g. layout) of the components and wires on the silicon is defined. Next is a post layout extraction stage 18, wherein an automatic approximate calculation may be performed for the wire non-ideal properties, which usually includes wire capacitance to ground, and in some instances, also for the cross capacitance between wires as well as the wire resistance. In other instances, the wire inductance may also be extracted. In the final stage, simulation 20, all elements, including the extracted wire parameters from stage 18, are simulated and compared to the original design requirements.
If the results of simulation 20 are slightly different from the design requirements, the designer may return to stage 16, repeating that stage and the following stages. However, if the results of simulation 20 are much different from the required results, which may happen, especially with high speed designs, the designer may not be able to salvage the physical design, and may find that it is easier and less time consuming to redesign the system, rather than try and modify the existing design. In this case, the designer may find himself returning to stage 14, and having to perform an almost total redesign.
In order to avoid such time-wasting efforts, it is the practice of highly experienced designers to try and somehow estimate the impacts of the main interconnects already in schematic design stage 14. In multi-GHz design regimes, on-chip interconnects may have a major impact on an integrated circuit (IC) performance, and produce thereto large time delays, overshoots, ringing effects, dispersion, etc. The common practice is therefore to try, during the extraction stage 18, to estimate the delay produced by the interconnect, and thus compensate for the interconnect impact. There have been partial successes in estimating the and capacitance (C) and resistance (R) effect, however, disappointingly, it has proved very difficult to estimate the inductance (L) effect, and the cross-capacitance (xC) effect, since an accurate extraction of the inductance requires the knowledge of the return path current for each wire, which is impossible at post layout stage without making very simplifying assumptions that lead to large errors. In multi-GHz designs, the inductance effect has proven to have a large impact, and traditional post-layout treatment of on-chip interconnects still leads to either numerous design iterations and consequently to longer time-to-market, or to a significant amount of over-design. There therefore exists a need to provide efficient and effective AMS design methodology.